Hysteresis characteristics are used in digital logic circuits to reduce/eliminate input noise to prevent false signals and glitches. A differential input receiver is essentially used for high-speed differential signaling. As the signaling speed is very high, the potential for noise induced interference is higher than for the normal case. Further differential IO standards generally require a low voltage input swing, e.g. for Low Voltage Differential Signals (LVDS) the minimum input voltage swing is 100 mV, as a result any small noise in the input can have a significant effect. For this reason, IEEE standard 1596.3-1996, for LVDS for Scalable Coherent Interface (SCI) recommends a minimum of 25 mV hysteresis in the LVDS receiver. Since LVDS signaling can operate over a wide range of input signals, it is necessary that the width of the hysteresis should be almost constant over that range.
FIG. 1 shows a differential input receiver in accordance with U.S. Pat. No. 6,275,073. This differential input circuit does not incorporate any hysteresis characteristics. The circuit can operate over a wide input range and can be used to support differential standards such as LVDS. The differential input circuit of FIG.1 includes a current mirror constant current source comprising a PMOS differential amplifier, and an NMOS differential amplifier. P_in and N_in are the two differential inputs to the circuits. PMOS transistors, Tr1 Tr2 and Tr3 and NMOS transistors, Tr9 and Tr10 constitute a PMOS differential amplifier while NMOS transistors Tr4, Tr5 and Tr6 and PMOS transistors Tr7 and Tr8 constitute an NMOS differential amplifier.
Transistors Tr2, Tr3, Tr5 and Tr6 are input transistors as their gates are connected to the input signals P_in and N_in. The source of transistors Tr2 and Tr3 are connected to the drain of transistor Tr1 whose gate is connected to VSS and source to VDD. VDD and VSS are the lower power supply terminals. The drain terminals of transistors Tr2 and Tr3 are connected to the drains of transistors Tr9 and Tr10 respectively. The source terminals of transistors Tr9 and Tr10 are connected together to the VSS. The gates of transistors Tr9 and Tr10 are connected to the drain of input transistor Tr2. The source terminals of transistors Tr5 and Tr6 are connected together to the drain of transistors Tr4, which has its gate connected to VDD while its source is connected to VSS. The drains of transistors Tr5 and Tr6 are connected to the drains of transistors Tr7 and Tr8 respectively whose source terminals are connected to VDD. The gates of transistors Tr7 and Tr8 are connected to the drain of input transistor Tr5. A resistance R is connected between the drains of transistors Tr2 and Tr5 while the drain terminals of transistors Tr3 and Tr6 are connected together to the output terminal Out.
The operation of the differential input receiver of FIG.1 can be understood as follows. When P_in is greater than N_in i.e. P_in>N_in, the output Out is HIGH. On other hand when P_in is less than N_in (P_in<N_in), Out is LOW. In this manner, the differential input receiver acts as a comparator and the switching point of the circuit is the cross-over point of the two differential inputs. If there is noise in any of the input signals that results in the crossing of two inputs, the output can switch to a false state. This is significant because the differential input receiver normally works at high frequencies where the potential noise influence is much greater. The output characteristics of this circuit are shown in FIG. 3 by the curve OUT_prior.
FIG. 1A shows the another prior art input receiver for Gunning Transceiver Logic (GTL) standard which is shown in U.S. Pat. No. 5,666,068 titled GTL Input Receiver With Hysteresis. This input receiver incorporates hysteresis to support GTL standard. This circuit is basically a PMOS differential amplifier where Vin1 and Vin2 are the two inputs and OUT is the output. PMOS P3 and PMOS P4 are the input transistors which are connected to the inputs. P8 and P9 transistors connected in parallel with P3 and P4 respectively are used to provide hysteresis. This circuit supports GTL standard only and can not be used to support LVDS standard.
Therefore, it has been observed that there is a need to develop an input receiver that incorporates hysteresis properties to eliminate the influence of noise signals while operating with low voltage swing and wide range of inputs.